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gs81314ld19/37gk-933/800 144mb sigmaquad-ive? burst of 4 single-bank eccram? up to 933 mhz 1.2v ~ 1.3v v dd 1.2v ~ 1.3v v ddq rev: 1.02 3/2016 1/39 ? 2015, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. 260-pin bga com & ind temp hstl i/o features ? 4mb x 36 and 8mb x 18 organizations available ? organized as a single logical memory bank ? 933 mhz maximum operating frequency ? 933 mt/s peak transaction rate (in millions per second) ? 134 gb/s peak data bandwidth (in x36 devices) ? separate i/o ddr data buses ? non-multiplexed sdr address bus ? one operation - read or write - per clock cycle ? no address/bank restrictions on read and write ops ? burst of 4 read and write operations ? 5 cycle read latency ? on-chip ecc with virtually zero ser ? loopback signal timing training capability ? 1.2v ~ 1.3v nominal core voltage ? 1.2v ~ 1.3v hstl i/o interface ? configuration registers ? configurable odt (on-die termination) ? zq pin for programma ble driver impedance ? zt pin for programmable odt impedance ? ieee 1149.1 jtag-compliant boundary scan ? 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 rohs- ? compliant bga package sigmaquad-ive ? family overview sigmaquad-ive eccrams are the separate i/o half of the sigmaquad-ive/sigmaddr-ive family of high performance eccrams. although similar to gsi's third generation of networking srams (the sigmaquad-iiie/sigmaddr-iiie family), these fourth generation devices offer several new features that help enable si gnificantly higher performance. clocking and addr essing schemes the gs81314ld19/37gk sigmaquad-ive eccrams are synchronous devices. they employ three pairs of positive and negative input clocks; one pair of master clocks, ck and ck , and two pairs of write data clocks, kd[1:0] and kd [1:0]. all six input clocks are single-ended; that is, each is received by a dedicated input buffer. ck and ck are used to latch address and control inputs, and to control all output timing. kd[1:0] and kd [1:0] are used solely to latch data inputs. each internal read and write operation in a sigmaquad-ive b4 eccram is four times wider than the device i/o bus. an input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. an output data multiplexer is used to capture the data produced from a single memory array r ead and then route it to the appropriate output drivers as needed. therefore, the address field of a sigmaquad-ive b4 eccram is always two address pins less than the advertised index depth (e.g. the 8m x 18 has 2m addressable index). on-chip error correction code gsi's eccrams implement an ecc algorithm that detects and corrects all single-bit me mory errors, including those induced by ser events such as cosmic rays, alpha particles, etc. the resulting soft error rate of these devices is anticipated to be <0.002 fits/mb ? a 5-order-of-magnitude improvement over comparable srams with no on-chip ecc, which typically have an ser of 200 fits/mb or more. all quoted ser values are at sea level in new york city. parameter synopsis speed grade max operating frequency read latency v dd -933 933 mhz 5 cycles 1.25v to 1.35v -800 800 mhz 5 cycles 1.15v to 1.35v
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 2/39 ? 2015, gsi technology 8m x 18 pinout (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 a v dd v ddq v dd v ddq nc (rsvd) mch (cfg) mrw zq pzt1 v ddq v dd v ddq v dd b v ss nu o v ss nu i mcl mch (b4m) nc (rsvd) mch (siom) pzt0 d0 v ss q0 v ss c q17 v ddq d17 v ddq v ss sa13 v dd sa14 v ss v ddq nu i v ddq nu o d v ss nu o v ss nu i sa19 v ddq nc (288 mb) v ddq sa20 d1 v ss q1 v ss e q16 v ddq d16 v dd v ss sa11 v ss sa12 v ss v dd nu i v ddq nu o f v ss nu o v ss nu i sa17 v dd v ddq v dd sa18 d2 v ss q2 v ss g q15 nu o d15 nu i v ss sa9 mzt1 sa10 v ss d3 nu i q3 nu o h q14 v ddq d14 v ddq sa15 v ddq w v ddq sa16 v ddq nu i v ddq nu o j v ss nu o v ss nu i v ss sa7 v ss sa8 v ss d4 v ss q4 v ss k cq1 v ddq v ref v dd kd1 v dd ck v dd kd0 v dd v ref v ddq cq0 l cq1 v ss qvld1 v ss kd 1 v ddq ck v ddq kd 0 v ss qvld0 v ss cq 0 m v ss q13 v ss d13 v ss sa5 v ss sa6 v ss nu i v ss nu o v ss n nu o v ddq nu i v ddq pll v ddq r v ddq mcl v ddq d5 v ddq q5 p nu o q12 nu i d12 v ss sa3 mzt0 sa4 v ss nu i d6 nu o q6 r v ss q11 v ss d11 mch v dd v ddq v dd rst nu i v ss nu o v ss t nu o v ddq nu i v dd v ss sa1 v ss sa2 v ss v dd d7 v ddq q7 u v ss q10 v ss d10 nc (576 mb) v ddq nc (rsvd) v ddq nc (1152 mb) nu i v ss nu o v ss v nu o v ddq nu i v ddq v ss sa21 (x18) v dd nu i (b2) v ss v ddq d8 v ddq q8 w v ss q9 v ss d9 tck mcl rcs mcl tms nu i v ss nu o v ss y v dd v ddq v dd v ddq tdo zt nc (rsvd) mcl tdi v ddq v dd v ddq v dd notes: 1. pins 5b, 6w, 8w, 8y, and 9n must be tied low in this device. 2. pin 5r must be tied high in this device. 3. pin 6a is defined as mode pin cfg in t he p i nout standard. it must be tied high in this device to select x18 configuration. 4. pin 6b is defined as mode pin b4m in the pinout standard. it must be tied high in this device to select burst-of-4 configurat ion. 5. pin 8b is defined as mode pin siom in the pinout standard. it mu st be tied high in this device to select separate i / o configu ration. 6. pin 6v is defined as address pin sa fo r x18 devices. it is used in this device . 7. pin 8v is defined as address pin sa for b2 devices. it is unused in this device , and must be left unconnected or driven low. 8. pin 7d is reserved as address pin sa for 288 mb devices. it is a true no connect in this device. 9. pin 5u is reserved as address pin sa for 576 mb devices. it is a true no connect in this device. 10. pin 9u is reserved as address pin sa for 1152 mb devices. it is a true no connect in this device.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 3/39 ? 2015, gsi technology 4m x 36 pinout (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 a v dd v ddq v dd v ddq nc (rsvd) mcl (cfg) mrw zq pzt1 v ddq v dd v ddq v dd b v ss q35 v ss d35 mcl mch (b4m) nc (rsvd) mch (siom) pzt0 d0 v ss q0 v ss c q26 v ddq d26 v ddq v ss sa13 v dd sa14 v ss v ddq d9 v ddq q9 d v ss q34 v ss d34 sa19 v ddq nc (288 mb) v ddq sa20 d1 v ss q1 v ss e q25 v ddq d25 v dd v ss sa11 v ss sa12 v ss v dd d10 v ddq q10 f v ss q33 v ss d33 sa17 v dd v ddq v dd sa18 d2 v ss q2 v ss g q24 q32 d24 d32 v ss sa9 mzt1 sa10 v ss d3 d11 q3 q11 h q23 v ddq d23 v ddq sa15 v ddq w v ddq sa16 v ddq d12 v ddq q12 j v ss q31 v ss d31 v ss sa7 v ss sa8 v ss d4 v ss q4 v ss k cq1 v ddq v ref v dd kd1 v dd ck v dd kd0 v dd v ref v ddq cq0 l cq 1 v ss qvld1 v ss kd 1 v ddq ck v ddq kd 0 v ss qvld0 v ss cq 0 m v ss q22 v ss d22 v ss sa5 v ss sa6 v ss d13 v ss q13 v ss n q30 v ddq d30 v ddq pll v ddq r v ddq mcl v ddq d5 v ddq q5 p q29 q21 d29 d21 v ss sa3 mzt0 sa4 v ss d14 d6 q14 q6 r v ss q20 v ss d20 mch v dd v ddq v dd rst d15 v ss q15 v ss t q28 v ddq d28 v dd v ss sa1 v ss sa2 v ss v dd d7 v ddq q7 u v ss q19 v ss d19 nc (576 mb) v ddq nc (rsvd) v ddq nc (1152 mb) d16 v ss q16 v ss v q27 v ddq d27 v ddq v ss nu i (x18) v dd nu i (b2) v ss v ddq d8 v ddq q8 w v ss q18 v ss d18 tck mcl rcs mcl tms d17 v ss q17 v ss y v dd v ddq v dd v ddq tdo zt nc (rsvd) mcl tdi v ddq v dd v ddq v dd notes: 1. pins 5b, 6w, 8w, 8y, and 9n must be tied low in this device. 2. pin 5r must be tied high in this device. 3. pin 6a is defined as mode pin cfg in t he p i nout standard. it must be tied low in this device to select x36 configuration. 4. pin 6b is defined as mode pin b4m in the pinout standard. it must be tied high in this device to select burst-of-4 configurat ion. 5. pin 8b is defined as mode pin siom in the pinout standard. it mu st be tied high in this device to select separate i / o configu ration. 6. pin 6v is defined as address pin sa for x18 devices. it is unused in this device, and must be left uncon nected or driven low . 7. pin 8v is defined as address pin sa for b2 devices. it is unused in this device , and must be left unconnected or driven low. 8. pin 7d is reserved as address pin sa for 288 mb devices. it is a true no connect in this device. 9. pin 5u is reserved as address pin sa for 576 mb devices. it is a true no connect in this device. 10. pin 9u is reserved as address pin sa for 1152 mb devices. it is a true no connect in this device.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 4/39 ? 2015, gsi technology pin description symbol description type sa[21:1] address ? read or write address is registered on ? ck. input d[35:0] write data ? registered on ? kd and ? kd during write operations. d[17:0] - x18 and x36. d[35:18] - x36 only. input q[35:0] read data ? aligned with ? cq and ? cq during read operations. q[17:0] - x18 and x36. q[35:18] - x36 only. output qvld[1:0] read data valid ? driven high one half cycle before valid read da ta. output ck, ck primary input clocks ? dual single-ended. used for latching addres s and control inputs, for internal timing control, and for output timing control. input kd[1:0], kd [1:0] write data input clocks ? dual single-ended. used for latching write data inputs. kd0, kd 0: latch d[17:0] in x36, and d[8:0] in x18. kd1, kd 1: latch d[35:18] in x36, and d[17:9] in x18. input cq[1:0], cq [1:0] read data output clocks ? fre e-running output (echo) clocks, tightly aligned with read data outputs. facilitate source-synchronous operation. cq0, cq 0: align with q[17:0] in x36, and q[8:0] in x18. cq1, cq 1: align with q[35:18] in x36, and q[17:9] in x18. output r read enable ? registered on ? ck. see the clock truth table for functionality. input w write enable ? registered on ? ck. see the clock truth table for functionality. input mrw mode register write ? registe red on ? ck. can be used synchronously or asynchronously to enable reg - ister write mode. see the state and cl ock t ruth tables for functionality. input pll pll enable ? w eakly pulled high internally. pll = 0: disables internal pll. pll = 1: enables internal pll. input rst reset ? holds the device inactive and reset s the device to its initial power-on state when asserted high. weakly pulled low internally. input zq driver impedance control resistor input ? must be connected to v ss through an external resistor rq to program driver impedance. input zt odt impedance control resistor input ? must be connected to v ss through an external resistor rt to program odt impedance. input rcs current source resistor input ? must be connected to v ss through an external 2k ? resistor to provide an accurate current source for the pll. input
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 5/39 ? 2015, gsi technology mzt[1:0] odt mode select ? set the default odt state globally for all input groups during power-up and reset. must be tied high or low. mzt[1:0] = 00: disables odt on all input groups, regardless of pzt[1:0]. mzt[1:0] = 01: enables strong odt on select input groups, as specified by pzt[1:0]. mzt[1:0] = 10: enables weak odt on select input group s, as specified by pzt[1:0]. mzt[1:0] = 11: reserved. note : the odt state for each input group can be changed at any time via the configuration registers. input pzt[1:0] odt configuration select ? set the default odt state for various combinations of input groups during power-up and reset, when mzt[1:0] = 01 or 10. must be tied high or low. pzt[1:0] = 00: enables odt on write data only. pzt[1:0] = 01: enables odt on write data and input clocks. pzt[1:0] = 10: enables odt on wr ite data, address, and control. pzt[1:0] = 11: enables odt on write data, input clocks, address, and control. note : the odt state for each input group can be changed at any time via the configuration registers. input v dd core power supply ? v ddq i/o power supply ? v ref input reference voltage ? input buffer reference voltage. ? v ss ground ? tck jtag clock ? w eakly pulled low internally. input tms jtag mode select ? weakly pulled high internally. input tdi jtag data input ? w eakly pulled high internally. input tdo jtag data output output mch must connect high ? may be tied to v ddq directly or via a 1k ? resistor. input mcl must connect low ? may be tie d to v ss directly or via a 1k? resistor. input nc no connect ? there is no intern al chip connection to t hese pins. they may be left unconnected, or tied/ driven high or low. ? nu i not used input ? there is an internal chip connection to t hese input pins, but they are unused by the device. they are pulled low internally. they may be left unconnected or tied/driven low. they should not be tied/driven high. input nu o not used output ? there is an internal chip connection to t hese output pins, but they are unused by the device. the drivers are tri-stated in ternally. they should be left unconnected. output symbol description type
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 6/39 ? 2015, gsi technology initialization summary prior to functional use, these devices must first be initialized and configured. the steps describe d below will ensure that the internal logic has been properly reset, and that functiona l timing parameters have been configured appropriately. flow chart power-up reset sram training required? address / control input training read data output training write data input training normal operation train again? yes no no yes enable pll, wait for lock additional wait for calibrations configuration notes : 1. mzt[1:0] and pzt[1:0] mode pins are used to set the default odt state of all input groups at power-up, and whenever rst is asserted high. the odt state for each input group can be changed any time thereafter using register write mode to program certain bits in the configuration registers. 2. calibrations are performed for driv er impedance, odt impedance, and the pll current source immediately after rst is de-asserted low. the calibrations can take up to 384k cycles total. see the power-up and reset requirements section for more information. 3. the pll can be enabled by the pll pin, or by the pll enable (ple) bit in the configuration registers. see the pll operation section for more information. 4. if the ple register bit is used to enable the pll, then register write mode will likely have to be utilized in the ?asynchronous, pre-input training? method in order to change the state of the bit, since address / control input training has not yet been performed. see the configurat ion registers section for more infor- mation. 5. it can take up to 64k cycles for the pll to lock after it has been enabled. 6. special loopback modes are available in these devices to perform address / control input training; they are selected and enabled via the loopback mode select (lbk[1:0]) and loopback mode enable (lbke) bits in the configuration registers. 7. if loopback modes are used to perform address / control input training, then register write mode will likely have to be utilized in the ?asynchronous, pre-input training? method in order to change the states of the lbk[1:0] and lbke register bits. 8. loopback modes can also be used for read data output training, if desired. see the signal timing training and loopback mode sections for more informa- tion. 9. ?additional configuration? includes programming the read latency to 5 cycles (which is required by these devices), and any other configuration changes required by the system. since this step is performed after address / control input training, register write mode can be utilized in the ?asynchronous, post-input training? method (or perhaps the ?synchronous? method, if the synchronous tim- ing requirements can be met at the particular operating frequency). 10. it is up to the system to determi ne if/when re-training is necessary.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 7/39 ? 2015, gsi technology power-up and r eset requirements for reliability purposes, power supplies must power up simultaneously, or in the following sequence: v ss , v dd , v ddq , v ref and inputs. power supplies must power down simultan eous ly, or in the reverse sequence. after power supplies power up, the followi ng start-up s equence must be followed. step 1 : assert rst high for at least 1ms. while rst is asserted high: ? the pll is disabled. ? the states of r , w , and mrw control inputs are ignored. note : if possible, rst should be asserted high before input clocks begin toggling, and remain asserted high until input clocks are stable and toggling within specification, in order to prevent un stable, out-of-spec input clocks from causing trouble in the sr am. step 2: begin toggling input clocks. after input clocks begin toggling, but not necessarily within specification: ? q are placed in the non-read state, and remain so until the fi rst read operation. ? qvld are driven low, and remain so until the first read operation. ? cq, cq begin toggling, but not nece ssarily within specification. step 3 : wait until input clocks are stable and toggling within specification. step 4 : de-assert rst low. step 5 : wait at least 384k (393,216) cycles. during this time: ? driver and odt impedances are calib rated. can take up to 320k cycles. ? the current source for the pll is calibrated (b ased on rcs pin). can take up to 64k cycles. step 6 : enable the pll. step 7 : wait at least 64k (65,536) cycles for the pll to lock. after the pll has locked: ? cq, cq begin toggling within specification. step 8 : continue initialization (see the initialization flow chart). reset usage although not generally recommended, rst may be asserted high at any time after completion of the initial power-up sequence described above, to reset the sram control logic to its initial power-on state. however, whenever rst is subsequently de-assert ed low, as in step 4 above, steps 5~7 above mu st be followed before normal operation is resumed. it is up the system to determine whether further re-initialization beyond step 7 (as outlined in th e initialization flow chart) is required before normal operat ion is resumed. note : memo ry array content may be perturbed/corrupted when rst is asserted high.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 8/39 ? 2015, gsi technology pll operation a pll is implemented in these devices to control all output timing. it uses the ck input clock as a source, and is enabled when all of the following conditions are met: 1. rst is de-asserted low, and 2. either the pll enable pin (pll) or the pll en able register bit (ple) is asserted high, and 3. ck cycle time ? t khkh (max), as specified in the ac timing specifications section. once enabled, the pll requires 64k stable clock cycles in order to lock/synchronize properly. when the pll is enabled, it aligns output clock s and read data to input clocks (w ith some fixed delay), and it generates all mid-cycle output timing. see the output timing section for more information. the pll can tolerate changes in input clock frequency due to clock jitter (i.e. such jitter will not cause the pll to lose lock / synchronization), provided th e cycle-to-cycle jitter does not exceed 200ps (see ?t kjitcc ? in the ac timing specifications section for more information). however, the pll must be resynchronized (i.e. disabled and then re-enabl ed) whenever th e nominal input clock frequency is changed. the pll is disabled when any of the following conditions are met: 1. rst is asserted high, or 2. both the pll enable pin (pll) and the pll en able register bit (ple) are deasserted low, or 3. ck is stopped for at least 30ns, or ck cycle time ? 3 0ns. on-chip error correction these devices implement a single-error corr ect, single-error detect (sec -sed) ecc algorithm (speci fically, a hamming code) on each 18-bit data word transmitted in ddr fashion on each 9-bit da ta bus (i.e., transmitted on d/ q[8:0], d/q[17:9], d/q[26:18], and d/q[35:27]). to accomplish this, 5 ecc pari ty bits (invisible to the user) are util ized per every 18 data bits (visible to the user). as such, these devices actuall y comprise 184mb of memory, of wh ich 144mb are visible to the user. the ecc algorithm cannot detect multi-bit errors. however, these dev ices are architected in such a way that a single ser event very rarely causes a multi-bit error acro ss any given ?transmitted data unit?, where a ?transmitted data unit? represents the d ata transmitted as the result of a single read or write operation to a particular address. the extrem e rarity of multi-bit errors r esults in the ser mentioned previously (i.e., <0.0 02 fits/mb, measured at sea level). not only does the on-chip ecc significantly improve ser performan ce, but it can also free up the entire memory array for data storage. very often sram applications allo cate 1/9th of the memory array (i.e., one ?er ror bit? per eight ?data bits?, in any 9 -bit ?data byte?) for error detection (either si mple parity error detection, or system-l evel ecc error detec tion and correction). depending on the application, such error-bit allocation may be unnecessary in these devices, in which case the entire memory ar ray can be utilized for data st orage, effectively providi ng 12.5% greater storage capacity compar ed to srams of the same density no t equipped with on-chip ecc.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 9/39 ? 2015, gsi technology configuration registers these devices utilize a set of registers for device conf iguration. the configuratio n registers are written via register write mode , which is initiated by asserting mrw high and r low. when register write mode is utilized, up to sixteen distinct 6-bit registers can be programmed using sdr timing on the sa[10:1] addr ess input pins. the d data input pins are not used. note : reg ister write mode only provides the ability to write the conf iguration registers. the ability to read the configuration regis - ters is provided via a private jtag instruction an d register. please contact gsi for more information. register write mode can be utilized in two ways: 1. as ynchronous method : mrw is driven asynchronously, such that is does not meet setup and hold time specs to ? ck. 2. synch ronous method : mrw is driven synchronously, such that is meets setup and hold time specs to ? ck. regardless how register write mode is utilized, at least 16 nops mu st be initiated before beginning a register write sequence, to ensure any previous read and write operations are completed befo re the sequence begins. and, at least 16 nops must be initiated after completing a register write sequence and before initiating read and write operations, and before utilizing loopback mode, to allow sufficient time for the newly progra mmed register settin gs to take effect. register write mode utiliz ation - asynchronous method register write mode can be utilized asynchronously up to the fu ll operating speed of the device. when register write mode is ut i - lized asynchronously, there are two ca ses to consider: 1. p re input training : sa[10:1], r , w are driven such that they do not meet setup and hold time specs to ? ck. 2. post input training : sa[10:1], r , w are driven such that they meet setup and hold time specs to ? ck. each case is examined separately below. pre input training requirements in this case, mrw, r , w , and sa[10:1] are all driven asynchronously. when regi ster write mode is utilized in this manner, only one register can be programmed during any partic ular instance that mr w is asserted high. the requirements for this usage case are as follows: ? at least 16 nops must be initiated be fore and after the r egister write sequence. ? mrw high must meet minimum pulse width requirements ( tmrwpw ). ? r low and sa[10:1] valid must meet minimum setup time requirements (tmrws) to mrw high. ? r low and sa[10:1] valid must meet minimum hold time requirements ( tmrwh ) from mrw low. ? w high must also meet minimum setup time requirements (tmrws) to mrw high, if inadvertent memory writes are to be pre - vented during the register write process. otherwise, w state is ?don?t care?. ? w high must also meet minimum hold time requirements ( tmrwh ) from mrw low, if inadvertent memory writes are to be prevented during the register write process. otherwise, w state is ?don?t care?. note : tmrwpw = tmrws = tmrwh = 4 cycles (minimum). note : inadvertent memory reads will occur while mrw and r are low during the register writ e process. the memory reads are harmless, and can be ignored.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 10/39 ? 2015, gsi technology post input training requirements in this case, mrw is driv en asynchronously , whereas r , w , and sa[10:1] are all dr iven synchronously (i.e. they all meet setup and hold time specs to ? ck). when register write mode is utilized in this manner, multiple registers can be programmed during any particular instance that mr w is asserted hi gh. the timing diagrams below arbitrarily show four registers programmed while mrw is asserted high, but in practice it can be any number greater th an or equal to one. the requirements for this usage case are as follows: ? at least 16 nops must be initiated before and after the register write(s). ? mrw high must meet minimum setup time requirements ( tmrws ) to the ? ck that generates the first register write. ? mrw high must meet minimum hold time requirements ( tmrwh ) from the ? ck that generates the first nop after the last reg - ister write. ? r must be driven low (synchronously) and sa[10:1] must be dr iven valid (synchr onously) for each register write. ? w state is a ?don?t care? (synchr onously) for each register write. note : tmrws = tmrwh = 4 cycles (minimum). asynchronous register write timi ng diagram - pre input training t mrwh ck w sa[10:1] register write mode register #n mrw t mrws t mrwpw r must be ?high? to prevent memory write; ?don?t care? otherwise 16 nops 16 nops asynchronous register write timi ng diagram - post input training ck sa[10:1] w register write mode 16 nops read / write read / write 16 nops reg #d reg #a mrw reg #b reg #c t ivkh t khix r t mrwh t mrws x x x x v vv v v v v v v
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 11/39 ? 2015, gsi technology register write mode util ization - synchronous method register write mode can also be utilized synchronously up to the full operating speed of the device. however, mrw cannot be trained using loopback mode, so the ability to use it synchronous ly may be limited to slower operating frequencies where the la ck of training capability is less problematic for the user. in this case, mrw, r , w , and sa[10:1] are all driven synchronously (i.e . they all meet setup and hold time specs to ? ck). when register w rite mode is utilized in this manner, multiple regi sters can be programmed in successi ve cycles. the timing diagrams below arbitrarily show four registers progra mmed in successive cycles, but in practice it can be any number greater than or equ al to one. the requirements for this usage case are as follows: ? at least 16 nops must be initiated before and after the register write(s). ? mrw must be driven high (synchronously), r must be driven low (synchronously), and sa[10:1] must be driven valid (syn - chronously) for each register w r ite. ? w state is a ?don?t care? (synchr onously) for each register write. synchronous register write timing diagram ck sa[10:1] w register write mode 16 nops read / write read / write 16 nops reg #d reg #a mrw reg #b reg #c t ivkh t khix t rvkh t khrx r x x x x v v v v v v v v v
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 12/39 ? 2015, gsi technology register description as described previously, register write mode provides the ability to program up to sixteen distinct 6-bit configuration registe rs us - ing sdr timing on the sa[10:1] address input pins. specifically, sa[4:1] are used to select one of the sixteen distinct registe rs, and sa[10:5] are used to program the six data bits of the selected register. the registers are defined as follows: address sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 reg # pin 8g 6g 8j 6j 8m 6m 8p 6p 8t 6t bit usage register data bits register select bits active rlm 0 0 0 0 0 active rsvd[2:0] ple 0 0 0 1 1 active lbk[1:0] lbke 0 0 1 0 2 active dzt[1:0] kdzt[1:0] ckzt[1:0] 0 0 1 1 3 active czt[1:0] azt[1:0] 0 1 0 0 4 unused all others except ?111x? 5 ~ 13 active reserved for gsi internal use only 1 1 1 x 14 ~ 15 notes : 1. unused/unlabeled register b its should be wri tten to ?0?. 2. the rsvd[2:0] bits in register #1 should be written to ?100?. 3. registers #14 and #15 are reserved for gsi internal use only. user s should not access these registers. register bit definitions read latency select pll enable rlm ple 0 read latency = 5 cycles 0 disable pll, if pll pin = 0 1 reserved 1 enable pll 1 por/rst default 0 por/rst default note : the po wer -on / reset default value of the rlm register bit is ?1 ?. consequently, register write mode must be used to set the rlm bit to ?0?, to program rl=5 in these devices, prior to issuing read operations.
loopback mode enable loopback mode select lbke lbk[1:0] 0 disable loopback mode 0 0 xor loopback mode, input group #1 1 enable loopback mode 0 1 xor loopback mode, input group #2 0 por/rst default 1 0 inv loopback mode, input group #1 1 1 inv loopback mode, input group #2 0 0 por/rst default gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 13/39 ? 2015, gsi technology note : in the odt control register bit definitions below, mzt[1:0] and pzt[1:0] pins set the default state of the register bits at p ow - er-up and whenever rst is assert ed high. the register bits can then be overwritten (via register write mode), while rst is de-a s - serted low, to change the state of the feature controlled by the register bits. input clock odt control address & contro l odt control ckzt1 ckzt0 azt1 azt0 kdzt1 kdzt0 czt1 czt0 0 0 disabled 0 0 disabled 0 1 enabled: pu = pd = rt 0 1 enabled: pu = pd = rt 1 0 enabled: pu = pd = 2*rt 1 0 enabled: pu = pd = 2*rt 1 1 reserved 1 1 reserved 00, if mzt[1:0] = 00 or pzt0 = 0 01, if mzt[1:0] = 01 and pzt0 = 1 10, if mzt[1:0] = 10 and pzt0 = 1 11, if mzt[1:0] = 11 and pzt0 = 1 por/rst default 00, if mzt[1:0] = 00 or pzt1 = 0 01, if mzt[1:0] = 01 and pzt1 = 1 10, if mzt[1:0] = 10 and pzt1 = 1 11, if mzt[1:0] = 11 and pzt1 = 1 por/rst default write data odt control dzt1 dzt0 0 0 disabled 0 1 enabled: pu = pd = rt 1 0 enabled: pu = pd = 2*rt 1 1 reserved 00, if mzt[1:0] = 00 01, if mzt[1:0] = 01 10, if mzt[1:0] = 10 11, if mzt[1:0] = 11 por/rst default
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 14/39 ? 2015, gsi technology signal timing training signal timing training (aka ?deskew?) is often required for re liable signal transmission between components at the i/o speeds supported by these devices. typically, the timing training is performed in the following sequence: step 1: address / control input training. ? these devices support a special loopback mode of operat ion to facilitate address / control input training. step 2: read data output training. ? these devices support a special loopback mode of oper at ion to facilitate read data output training. ? alternatively, slow-frequency memory w rite operations can be used to store ddr data patterns in the memory array reliably (full-frequency memory write operations cannot be us ed because write data signals have not been trained yet), and full-frequency memory read operations can then be used to train the read data output signals. step 3: write data input training. ? since address, control, and read data si gnals have already been trained at this point, full-frequency memory write and read operations can then be used to train the write data inputs. loopback mode these devices support two distinct loopback modes of operation, which can be used to: 1. perform per-pin training on the address (sa), control ( r , w ), and write data clock (kd, kd ) inputs. 2. perform per-pin training on the read data (q) outputs. in both cases, sa, r , w , kd, kd input pin values are sampled, logically manipulated, and looped back to q output pins. register bit lbke is used to enable/dis able loopback mode. wh en lb ke = 1 and mrw = 0, loopback mode is enabled, and memory read and write operations are blocked regardless of the states of r and w . when lbke = 0 or mrw = 1, loopback mode is disabled. see the state truth table for more information. register bits lbk[1:0] are used to select between the two distinct loopback modes supported by the design (controlled by lbk1), and bet ween the two groups of inputs used during the se lected loopback mode (controlled by lbk0), as follows: ? lbk[1:0] = 00: selects xor lbk mode using input group 1. loopback mode ?00?. ? lbk[1:0] = 01: selects xor lbk mode using input group 2. loopback mode ?01?. ? lbk[1:0] = 10: selects inv lbk mode us in g input group 1. loopback mode ?10?. ? lbk[1:0] = 11: selects inv lbk mode usin g input group 2. loopback mode ?11?. note : for convenience, kd clocks have been in cluded in the group of inputs that can be trained via loopback mode. however, ? the timing requirement for kd clocks is that their edges be tig htl y aligned to ck clock edges, unlike the timing requirement fo r address/control signals, whose edges must be centered (approxi mately) between ck edges in order to optimize setup and hold times to those ck edges. consequently, it is questionable whether loopback mode can be used to train kd clocks effectively. loopback latency loopback latency (?lbkl?) - i.e. the number of cycles from when the inputs are sampled to when the proper result appears on the output pins, is equal to 7 cycles. enabling loopback mode loopback mode is enabled as follows: step 1: initiate a register write operation with sa[10:1] = ?000ab1.0010? to select register #2, set lbke = 1 to enable loopb ack mode, and set lbk[1:0] to ?ab? to select loopback mode ?ab?. step 2: wait 16 cycles for new regi ster settings to take effect. loopback mode ?ab? is enabled after step 2 becau se mr w = 0, lbke = 1, and lbk[1:0] = ?ab?.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 15/39 ? 2015, gsi technology changing loopback modes once enabled, loopback mode can be changed as follows step 1: initiate a register writ e op eration with sa[10:1] = ?000cd1.0010? to select register #2, keep lbke = 1 to keep loopback mode enabled, and set lbk[1:0] to ?cd? to select loopback mode ?cd?. step 2: wait 16 cycles for new regi ster settings to take effect. loopback mode ?cd? is enabled after step 2 becau se mr w = 0, lbke = 1, and lbk[1:0] = ?cd?. disabling loopback mode loopback mode is disabled as follows: step 1: initiate a register write operation with sa[10:1] = ?000xx0.0010? to select register #2 and set lbke = 0 to disable loopb ack mode. step 2: wait 16 cycles for new regi ster settings to take effect. loopback mode is disabled after step 2 because lbke = 0. xor lbk mode xor lbk mode is for address/control input training . it is defined as follows: ? each input pin of the selected input group is sampled on ? ck and ? ck . ? for each input sampled, the value sampled on ? ck is xored with the value sampled on ? ck . ? for each input sampled, the xor result is subsequently dr iven out on its associated ou tput pin (concurrently with ? cq) for one fu ll clock cycle, beginning ?lbkl? cy cles after the input is sampled. consequently, the output data pattern is always sdr regardless of the inp ut data pattern, and regardless whether the sram samples the inputs correctly or not. the sdr output data pattern enables address/control inputs to be trained before data outpu ts. xor lbk mode enables the controller to input various sdr and ddr data patterns on a particular input, and then determine whether the sram sampled them correctly or not by observing sdr data patterns on the associated output. via multiple iterations of this process, the controller can adjust its output timing (in order to adjust the sram input timing) until optimum setup and hold margin at both sram input sample points is achieved, ther eby individually ?training? each address/control input pin. inv lbk mode inv lbk mode is primarily for read data output training . it is defined as follows: ? each input pin of the selected input group is sampled on ? ck and ? ck . ? for each input sampled, the value sampled on ? ck is subsequently driven out on its associated output pin (concurrently with ? cq) for half a clock cycle, beginning ?lbkl? cycles after the input is sampled. ? for each input sampled, the value sampled on ? ck is inverted and then subsequently driven out on its associated output pin (con - currently with ? cq ) for half a clock cycle, beginning ?lbkl + 0.5? cycles after the input is sampled. consequently, the output data pattern is ddr if the input data pattern is sdr (and vice versa), provided the sram samples the inputs correctly. therefore, to ensure dete rministic output behavior, address/control inputs should be trained before data outp uts. inv lbk mode enables the controller to input various sdr (or ddr) d ata patterns on a particular input, to generate deterministi c ddr (or sdr) data patterns on a particular output. the controller latches the output as it would during a normal read operation , and verifies whether it received the expected values or not. via multip le iterations of this process, the controller can adjust its input timing until optimum setup and hold margin at both controller inpu t sample points is achieved, thereby individually ?training? each read data output pin. note : inv lbk mode can be used for address/co ntrol input training, if desired. however, such usage can be problematic because the output data pattern may be erroneous (i.e. it could be sdr or ddr regardless of the input pattern) if the sram samples the input incorrectly. in which case the controller may have difficulty detecting the erroneous behavior, and/or interpreting it.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 16/39 ? 2015, gsi technology entering xor lbk mode ck 16 nops xor lbk mode 16 nops cq input register write mode output nop state output begins reflecting xor lbk result ... undefined (enable xor lbk) (first 6 cycles of 11, for example) exiting xor lbk mode ck xor lbk mode continued register write mode 16 nops cq input output ... after loopback latency undefined nop state (disable xor lbk) read / write (last 5 cycles of 11, for example) note : ?input? represents any loop-backed input pin. ?output? re presents the output pin on which ?input? is looped back.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 17/39 ? 2015, gsi technology entering inv lbk mode ck 16 nops inv lbk mode 16 nops cq input register write mode output nop state output begins reflecting inv lbk result ... undefined (enable inv lbk) (first 6 cycles of 11, for example) exiting inv lbk mode ck inv lbk mode continued register write mode 16 nops cq input output ... after loopback latency undefined nop state (disable inv lbk) read / write (last 5 cycles of 11, for example) note : ?input? represents any loop-backed input pin. ?output? re presents the output pin on which ?input? is looped back.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 18/39 ? 2015, gsi technology loopback mode input group definition and input-to-out put pin mapping inputs are divided into 2 groups because there are up to 28 input s to train (22 address, 2 contro l, and 4 kd clocks), but as fe w as 18 outputs available to loop them back to (in x18 devices). there are 18 inputs per group - one per q output in x18 devices, and one per two q outputs in x36 devices. bit # input pins input signals output pins output signals gp1 gp2 gp1 gp2 x18 x36 x18 x36 1 8p 8v sa4 nu 13v 13v, 12w q8 q8, q17 2 8m 8t sa6 sa2 13t 13t, 12u q7 q7, q16 right side output data byte(s) 3 8j --- sa8 rsvd 13p 13p, 12r q6 q6, q15 4 9h 9l sa16 kd 0 13n 13n, 12p q5 q5, q14 5 8g 9k sa10 kd0 12j 12j, 12m q4 q4, q13 6 9f 7h sa18 w 12g 12g, 13h q3 q3, q12 7 8e --- sa12 rsvd 12f 12f, 13g q2 q2, q11 8 9d --- sa20 rsvd 12d 12d, 13e q1 q1, q10 9 8c --- sa14 rsvd 12b 12b, 13c q0 q0, q9 10 6t --- sa1 rsvd 2w 2w, 1v q9 q18, q27 left side output data byte(s) 11 6p 6v sa3 sa21 2u 2u, 1t q10 q19, q28 12 6m --- sa5 rsvd 2r 2r, 1p q11 q20, q29 13 6j 7n sa7 r 2p 2p, 1n q12 q21, q30 14 5h 5l sa15 kd 1 2m 2m, 2j q13 q22, q31 15 6g 5k sa9 kd1 1h 1h, 2g q14 q23, q32 16 5f --- sa17 rsvd 1g 1g, 2f q15 q24, q33 17 6e --- sa11 rsvd 1e 1e, 2d q16 q25, q34 18 5d 6c sa19 sa13 1c 1c, 2b q17 q26, q35 notes : 1. blue shading indicates input pi ns that are unused (nu) in certain devi ce configurations. during loopback mode, the associated output pins loop back the states of those input pins regardless whether they are used or unused. 2. gray shading indicates group 2 inputs that are reserved (rs vd) for fut ure use. during loopback mode, the associated output pins act as if they were loop ing back input pins tied low. 3. the 18 unused q in x18 devices remain in their ?nu? states during loopback mode.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 19/39 ? 2015, gsi technology address bus utilization the address bus is a non-multiplexed sdr bus. one memory address may be loaded per cycle - a read address at ? ck or a write address at ? ck; consequently only one memory operation - a read or a write - may be initiated per clock cycle. the address bus is also sampled at ? ck during a regist er w r ite operation. address bit encoding command addr load device sa address bits 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read ? ck x36 nu address nu x18 address nu write ? ck x36 nu address nu x18 address nu register wr i te ? ck x36 nu x x x x x x x x x x register data register # nu x18 x x x x x x x x x x x register data register # nu read latency read latency (i.e. the number of cycles from read command input to first read data output) is specified as follows: read latency comment 5 cycles first read data output 5 cycles after read command input note : the rlm register bit must be written to ?0? in these devices pri or to initiating read operations, to set read latency = 5 cyc les. write latency write latency (i.e. the number of cycles from write command input to first writ e data input) is specified as follows: write latency comment -1 cycle first write date input 1 cycle before write command input read / write coherency these devices are fully coherent. that is, re ad operations always return the most recently written data to a particular address , even when a read operation to a particular address occurs one cycle after a wr ite operation to the same address.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 20/39 ? 2015, gsi technology state truth table rst mrw lbke r w sa d sram state q 1 x x x x x x reset nop state 0 1 x 0 x v x register write mode undefined 0 0 1 x x x x loopback mode loopback 0 1 x 1 see clock truth table memory mode (read, write, nop) see clock truth t able 0 0 0 x no te: 1 = high; 0 = low; v = v a lid; x = don?t care. clock truth table sa mrw r w previous operation current operation d q ? ck (t n ) ? ck (t n ) ? ck (t n ) ? ck (t n ) (t n?1 ) (t n ) ? kd (t n-1 ) ? kd (t n-? ) ? kd (t n ) ? kd (t n+? ) ? cq (t n+5 ) ? cq (t n+5? ) ? cq (t n+6 ) ? cq (t n+6? ) x 0 1 1 nop nop x x ? 0 ? x 0 1 x write nop d3 d4 ? 0 ? x 0 x 1 read nop x x ? q3 q4 ? v 0 1 0 nop write d1 d2 d3 d4 0 ? v 0 x 0 read write d1 d2 d3 d4 q3 q4 ? v 0 0 x nop read x x ? q1 q2 q3 q4 v 0 0 x write read d3 d4 ? q1 q2 q3 q4 v 1 0 x nop register write x x ? undefined undefined 1 1 x nop nop x x ? 0 ? notes: 1. 1 = high; 0 = low; v = valid; x = don?t care. 2. d1, d2, d3, and d4 indicate the first, second, third, and fourth pieces of write data tr ansferred during w rite operations. 3. q1, q2, q3, and q4 indicate the first, second, third, and fourth pieces of rea d data tr ansferred during read operations. 4. q pins are driven low for one cycle in response to nop and writ e commands, 5 cycles after the command is sampled, except when pre - ceded by a read command.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 21/39 ? 2015, gsi technology input timing these devices utilize three pairs of po sitive and negative input clocks, ck & ck and kd[1:0] & kd [1:0], to latch the various synchronous inputs. specifically: during memory mode, ? ck latches address (sa) inputs, and ? ck latches control ( r , w , mrw) inputs. during register write mode, ? ck latches address and control inputs. during loopback mode, ? ck and ? ck latch address, control, and write data clock (kd, kd ) inputs. during memory mode, ? kd[1:0] and ? kd [1:0] latch particular write data (d) inputs, as follows: ? ?? kd0 and ? kd 0 latch d[17:0] in x36 devices, and d[8:0] in x18 devices. ? ?? kd1 and ? kd 1 latch d[35:18] in x36 devices, and d[17:9] in x18 devices. output timing these devices provide two pairs of positive and ne gative output clocks (aka ?echo clocks?), cq[1:0] & cq [1:0], whose timing is tightly aligned with read data in order to enable reliable source-synchronous data transmission. these devices utilize a pll to co n trol output timing. when the pll is enabled, it generates 0 ? and 180 ? phase clocks from ? ck that control read data output clock (cq, cq ), read data (q), and read data valid (qvld) output timing, as follows: ? ?? ck+0 ? generates ? cq[1:0], ? cq [1:0], q1 active, and q2 inactive. ? ?? ck+180 ? gen erates ? cq [1:0], ? cq[1:0], q1 inactive, q2 activ e, and qvld ac tive/inactive. note : q1 and q2 indicate the first and second pieces of read data transferred in any given clock cycle during read operations. when the pll is enabled, ? cq is aligned to an internally-delayed version of ? ck. see the ac timing sp ecifications for more information. ? cq [1:0] and ? cq [1:0] align with particular q and qvld outputs, as follows: ? ?? cq 0 and ? cq0 align with q[17:0], qvld0 in x36 devices, and q[8:0], qvld0 in x18 devices. ? ?? cq 1 and ? cq1 align with q[35:18], qvld1 in x36 devices, and q[17:9], qvld0 in x18 devices.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 22/39 ? 2015, gsi technology driver impedance control programmable driver impedance is implemented on the following output signals: ? cq, cq , q, qvld. driver impedance is programmed by connecting an external re sist or rq between the zq pin and v ss . driver impedance is set to the programmed value within 320k cy c l es after input clocks are ope rating within specification and rs t is de-asserted low. it is updated periodically thereafter to comp ensate for temperature and voltag e fluctuations in the system. output signal pull-down impedance (r outl ) pull-up impedance (r outh ) cq, cq , q, qvld rq*0.2 ? 15% rq*0.2 ? 15% notes: 1. r outl and r outh apply when 175 ??? rq ? 225??. 2. the mismatch between r outl and r outh is less than 10%, guaranteed by design. odt impedance control programmable odt impedance is implemented on the following input signals: ? ck, ck , kd, kd , sa, r , w , mrw, d. odt impedance is programmed by connecting an ex t e rnal resistor rt between the zt pin and v ss . odt impedance is set to the programmed va lue within 320k cycles afte r input clocks are operating within specification and rst is de-asserted low. it is updated periodically thereafter to comp ensate for temperature and voltag e fluctuations in the system. input signal register bits pull-down impedance (r inl ) pull-up impedance (r inh ) ck, ck ckzt[1:0] = 00 off off ckzt[1:0] = 01 rt ? 15% rt ? 15% ckzt[1:0] = 10 rt*2 ? 20% rt*2 ? 20% ckzt[1:0] = 11 reserved reserved kd, kd kdzt[1:0] = 00 off off kdzt[1:0] = 01 rt ? 15% rt ? 15% kdzt[1:0] = 10 rt*2 ? 20% rt*2 ? 20% kdzt[1:0] = 11 reserved reserved sa azt[1:0] = 00 off off azt[1:0] = 01 rt ? 15% rt ? 15% azt[1:0] = 10 rt*2 ? 20% rt*2 ? 20% azt[1:0] = 11 reserved reserved
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 23/39 ? 2015, gsi technology note: when odt impedance is enabled on a particular input, that input should always be driven high or low; it should never be tri-stated (i.e., in a high- z st ate). if the input is tri-stated, the odt will pull the signal to v ddq / 2 (i.e., to the switch point of the diff-amp receiver), which could cause the r eceiver to enter a meta-stable state and cons ume more power than it normally would. this could result in the device?s operating currents being higher. r , w , mrw czt[1:0] = 00 off off czt[1:0] = 01 rt ? 15% rt ? 15% czt[1:0] = 10 rt*2 ? 20% rt*2 ? 20% czt[1:0] = 11 reserved reserved d dzt[1:0] = 00 off off dzt[1:0] = 01 rt ? 15% rt ? 15% dzt[1:0] = 10 rt*2 ? 20% rt*2 ? 20% dzt[1:0] = 11 reserved reserved notes: 1. r inl and r inh apply when 105 ??? rt ? 135?? 2. the mismatch between r inl and r inh is less than 10%, guaranteed by design. 3. all odt is disabled during jtag extest and sample-z instructions. input signal register bits pull-down impedance (r inl ) pull-up impedance (r inh )
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 24/39 ? 2015, gsi technology absolute maximum ratings parameter symbol rating units notes core supply voltage v dd -0.3 to +1.4 v i/o supply voltage v ddq -0.3 to v dd v input voltage (hs) v in1 -0.3 to v ddq + 0.3 v 2 v in2 v ddq - 1.5 to +1.7 input voltage (ls) v in3 -0.3 to v ddq + 0.3 v 3 junction temperature t j 0 to 125 ? c storage temperature t stg -55 to 125 ? c notes: 1. permanent damage to the device may occur if the absolute maximu m ratin gs are exceede d. operation should be restricted to reco m - mended operating conditions. exposure to conditions exceeding the recommended operati ng conditions for an extended period of ti me may affect reliability of this component. 2. parameters apply to high speed inputs: ck, ck , kd, kd , sa, d, r , w , mrw. v in1 and v in2 must both be met. 3. parameters apply to low speed inputs: rst, pll, mzt, pzt. recommended oper ating conditions parameter symbol min typ max units notes core supply voltage (-933 speed grade) v dd 1.25 1.3 1.35 v core supply voltage (-800 speed grade) v dd 1.15 1.2 1.35 v i/o supply voltage v ddq 1.15 1.2 v dd v commercial junction temperature t jc 0 ? 85 ? c industrial junction temperature t ji -40 ? 100 ? c note: for reliability purposes, power supplies must power up simultaneously , or in the following sequence: v ss , v dd , v ddq , v ref , and inputs. power supplies must power down simultaneously , or in the reverse sequence. thermal impedances package ?? ja (c/w) airflow = 0 m/s ? ja (c/w) airflow = 1 m/s ? ja (c/w) airflow = 2 m/s ?? jb (c/w) ? jc (c/w) fbga 13.67 10.28 9.31 3.08 0.13
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 25/39 ? 2015, gsi technology i/o capacitance parameter symbol min max units notes input capacitance c in ? 5.0 pf 1, 3 output capacitance c out ? 5.5 pf 2, 3 notes: 1. v in = v ddq /2. 2. v out = v ddq /2. 3. t a = 25? c, f = 1 mhz. input electrical characteristics parameter symbol min typ max units notes dc input reference voltage v refdc 0.48 * v ddq 0.50 * v ddq 0.52 * v ddq v ? dc input high voltage (hs) v ih1dc v ref + 0.08 0.80 * v ddq v ddq + 0.15 v 1, 6 dc input low voltage (hs) v il1dc -0.15 0.20 * v ddq v ref - 0.08 v 2, 6 dc input high voltage (ls) v ih2dc 0.75 * v ddq v ddq v ddq + 0.15 v 7 dc input low voltage (ls) v il2dc -0.15 0 0.25 * v ddq v 7 ac input reference voltage v refac 0.47 * v ddq 0.50 * v ddq 0.53 * v ddq v 3 ac input high voltage (hs) v ih1ac v ref + 0.15 0.80 * v ddq v ddq + 0.25 v 1, 4~6 ac input low voltage (hs) v il1ac -0.25 0.20 * v ddq v ref - 0.15 v 2, 4~6 ac input high voltage (ls) v ih2ac v ddq - 0.2 v ddq v ddq + 0.25 v 4, 7 ac input low voltage (ls) v il2ac -0.25 0 0.2 v 4, 7 notes: 1. ?typ? parameter applies when controller r outh = 40? and sram r inh = r inl = 120? . 2. ?typ? parameter applies when controller r outl = 40 ? and sram r inh = r inl = 120? . 3. v refac is equal to v refdc plus noise. 4. v ih max and v il min apply for pulse widths less than one-quarter of the cycle time. 5. input rise and fall times must be a minimum of 1v/ns, and within 10% of each other. 6. parameters apply to high speed inputs: ck, ck , kd, kd , sa, d, r , w , mrw. 7. parameters apply to low speed inputs: rst, pll, mzt, pzt.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 26/39 ? 2015, gsi technology output electrical characteristics parameter symbol min typ max units notes dc output high voltage v ohdc ? 0.80 * v ddq v ddq + 0.15 v 1, 3 dc output low voltage v oldc -0.15 0.20 * v ddq ? v 2, 3 ac output high voltage v ohac ? 0.80 * v ddq v ddq + 0.25 v 1, 3 ac output low voltage v olac -0.25 0.20 * v ddq ? v 2, 3 note: 1. ?typ? parameter applies when sram r outh = 40 ? and controller r inh = r inl = 120? . 2. ?typ? parameter applies when sram r outl = 40? and controller r inh = r inl = 120? . 3. parameters apply to: cq, cq , q, qvld. leakage currents parameter symbol min max units notes input leakage current i li1 -2 2 ua 1, 2 i li2 -20 2 ua 1, 3 i li3 -2 20 ua 1, 4 output leakage current i lo -2 2 ua 5, 6 notes: 1. v in = v ss to v ddq . 2. parameters apply to ck, ck , kd, kd , sa, d, r , w , mrw when odt is disabled. ? parameters apply to mzt, pzt. 3. parameters apply to pll, tms, tdi (weakly pulled up). 4. parameters apply to rst, tck (weakly pulled down). 5. v out = v ss to v ddq . 6. parameters apply to cq, cq , q, qvld, tdo.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 27/39 ? 2015, gsi technology operating currents parameter symbol v dd (nom) 800 mhz 933 mhz units x18 operating current i dd 1.3v 2050 2250 ma 1.2v 1800 ? ma x36 operating current i dd 1.3v 2700 2950 ma 1.2v 2450 ? ma notes: 1. i out = 0 ma; v in = v ih or v il . 2. applies at 100% alternating reads and writes. ac test conditions parameter symbol conditions units core supply voltage (-933 speed grade) v dd 1.25 to 1.35 v core supply voltage (-800 speed grade) v dd 1.15 to 1.35 v i/o supply voltage v ddq 1.15 to 1.25 v input reference voltage v ref 0.6 v input high level v ih 0.9 v input low level v il 0.3 v input rise and fall time ? 2.0 v/ns input and output reference level ? 0.6 v note: output load condit i ons rq = 200 ? . refer to figure below. ac test output load 50? v ddq /2 50? output 5 pf
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 28/39 ? 2015, gsi technology ac timing specifications (indep endent of device speed grade) parameter symbol min max units notes input clock timing clk high pulse width t khkl 0.45 ? cycles 1 clk low pulse width t klkh 0.45 ? cycles 1 clk high to clk high t kh k h 0.45 0.55 cycles 2 clk high to write data clk high t khkdh -200 +200 ps 3 clk cycle-to-cycle jitter t kjitcc ? 60 ps 1,4,5 pll lock time t klock 65,536 ? cycles 6 clk static to pll reset t kreset 30 ? ns 7,12 output timing clk high to output valid / hold t khqv/x +0.4 +1.2 ns 8 clk high to echo clock high t khcqh +0.4 +1.2 ns 9 echo clk high to output valid / hold t cqhqv/x -75 +75 ps 10,12 echo clk high to echo clock high t cqh cq h 0.5*t khkh (nom) - 25 0.5*t khkh (nom) + 25 ps 11,12 notes: all parameters are measured from the mid-point of the object signal to the mid-point of the reference signal. 1. parameters apply to ck, ck , kd, kd . 2. parameter specifies ? ? ck ?? ? ck and ? kd ?? ? kd requirements. 3. parameter specifies ? ck ?? ? kd and ? ck ? ?? kd requirements. 4. parameter specifies cy cle-to-c ycle (c2c) jitter (i.e. the maximum variation from cloc k rising edge to the next clock rising edge). ? as such, it limits period jitter (i. e. the maximum variation in clock cycle time from nominal) to ? 30ps. ? and as such, it limits absolute jitter (i.e. the maximum variation in clock rising edge from its nominal po sition) to ? 15ps. 5. the device can tolerated c2c jitter greater than 60ps, up to a maximu m of 200ps. however , when using a device from a particul ar speed grade, t khkh (min) of that speed grade must be derated (increased) by half the difference between the actual c2c jitter and 60ps. for example, if the actual c2c jitter is 100ps, then t khkh (min) for the -933 speed grade is derated to 1.09ns (1.07ns + 0.5*(100ps - 60ps)). 6. v dd slew rate must be < 0.1v dc per 50ns for p ll lock retention. pll lock time begins once v dd and input clock are stable. 7. parameter applies to ck. 8. parameters apply to q, and are referenced to ? ck. 9. parameter specifies ? ck ?? ? cq timing. 10. parameters apply to q, qvld and are referenced to ? cq & ? cq . 11. parameter specifies ? cq ?? ? cq timing. t khkh (nom) is the nominal input cloc k cycle time applied to the device. 12. parameters are not tested. they are guaranteed by design, and verified through extens ive corner-lot characterization.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 29/39 ? 2015, gsi technology ac timing specificati ons (variable with device speed grade) parameter symbol ?933 ?800 units notes min max min max input clock timing clk cycle time t khkh 1.07 6.0 1.25 6.0 ns 1 input setup & hold timing input valid to clk high t ivkh 150 ? 150 ? ps 2 clk high to input hold t khix 150 ? 150 ? ps input pulse width t ipw 200 ? 200 ? ps 3 mrw valid to clk high t rvkh 150 ? 150 ? ps 4 clk high to mrw hold t khrx 150 ? 150 ? ps notes: all parameters are measured from the mid-point of the object signal to the mid-point of the reference signal. 1. parameters apply to ck, ck , kd, kd . 2. parameters apply to sa, and are referenced to ? ck (and to ? ck during loopback mode). ? parameters apply to r , w , and are referenced to ? ck (and to ? ck during loopback mode). ? parameters apply to d, and are referenced to ? kd & ? kd . ? parameters apply to kd, kd , and are referenced to ? ck & ? ck during loopback mode. 3. parameter specifies the input pulse width requirements for each individual addre s s, control, and data input. per-pin deskew m ust be per - formed, to center the valid window of each individual input aroun d the clock edge that latches it, in order for this parameter to be relevant to the application. the parameter is not tested; it is guaranteed by design and verified through extensive corner-lot character ization. 4. parameters apply to mrw, and are referenced to ? ck. applicable when register wr ite mode is utilized synchronously.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 30/39 ? 2015, gsi technology memory read and write timing diagram t khix t ivkh t khix t ivkh t khkdh t khkdh a6 ck ck sa q read write read nop nop write read write read write nop a2 a3 w a7 d a8 qvld kd kd r a4 a5 t khkh t khkl t klkh t khk h t khkh t khkl t klkh t khk h t khqv t khqx cq cq t cqhqv t cqhqx t cqhqv t cqhqx t cqhcq h t khcqh a1 q11 q12 q13 q14 q31 q32 d21 d22 d23 d24 d41 d42 d43 d44 d61 d62 d63 d64 d81 t khix t ivkh t khix t ivkh d82 d83 d84 q33 q34 note : mrw=0 (not shown).
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 31/39 ? 2015, gsi technology jtag test mode description these devices provide a jtag test access port (tap) and boundary scan interface us ing a limited set of ieee std. 1149.1 functions. this test mode is intended to provide a mechanism fo r testing the interconnect between master (proces sor, controller, etc.), eccram, other components, and the pr inted circuit board. in conformance with a subset of ieee std. 1149.1, these devices contain a tap controller and multiple tap registers. the tap regi sters consist of one instruction register and multiple data registers. the tap consists of the following four signals: pin pin name i/o description tck test clock i induces (clocks) tap controller state transitions. tms test mode select i inputs commands to the tap controller. sampled on the rising edge of tck. tdi test data in i inputs data serially to the tap registers. sampled on the rising edge of tck. tdo test data out o outputs data serially from the tap registers. driven from the falling edge of tck. concurrent tap and normal eccram operation according to ieee std. 1149.1, most public tap instructions do not disrupt normal de vice operation. in these devices, the only exceptions are extest and sample- z. see the tap registers s ection for more information. disabling the tap when jtag is not used, tck should be tied low to prevent clocking the eccram. tms and tdi should either be tied high through a pull-up resistor or left unconnected. tdo should be left unconnected. jtag dc operating conditions parameter symbol min max units notes jtag input high voltage v tih 0.75 * v ddq v ddq + 0.15 v 1 jtag input low voltage v til ?0.15 0.25 * v ddq v 1 jtag output high voltage v toh v ddq ? 0.2 ? v 2, 3 jtag output low voltage v tol ? 0.2 v 2, 4 notes: 1. parameters apply to tck, tms, and tdi. 2. parameters apply to tdo. 3. i toh = ?2.0 ma. 4. i tol = 2.0 ma.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 32/39 ? 2015, gsi technology jtag ac timing specifications parameter symbol min max units tck cycle time t thth 50 ? ns tck high pulse width t thtl 20 ? ns tck low pulse width t tlth 20 ? ns tms setup time t mvth 10 ? ns tms hold time t thmx 10 ? ns tdi setup time t dvth 10 ? ns tdi hold time t thdx 10 ? ns capture setup time (address, control, data, clock) t cs 10 ? ns capture hold time (address, control, data, clock) t ch 10 ? ns tck low to tdo valid t tlqv ? 10 ns tck low to tdo hold t tlqx 0 ? ns jtag timing diagram t thtl t tlth t thth t thmx t mvth t thdx t dvth t tlqv t tlqx tck tms tditdi tdo
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 33/39 ? 2015, gsi technology tap controller the tap controller is a 16-state state machine that controls access to the various tap registers and executes the operations associated with each tap instruction. st ate transitions are controlled by tms an d occur on the rising edge of tck. the tap controller enters the test-logic reset state in one of two ways: 1. at power up. 2. when a logic 1 is applied to tms for at least 5 cons ecutive rising edges of tck. the tdi input receiver is sampled only wh en the tap controller is in either th e shift-ir state or the shift-dr state. the tdo output driver is enabled only when the tap controller is in eit h er the shift-ir state or the shift-dr state. tap controller state diagram test-logic reset run-test / idle select dr-scan select ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 34/39 ? 2015, gsi technology tap registers tap registers are serial shift registers that capture serial input data (from tdi) on th e rising edge of tck, and drive serial output data (to tdo) on the subsequent falling edge of tck. they ar e divided into two groups: instruction registers (ir), which are manipulated via the ir states in the tap controller, and data re gisters (dr), which are manipulate d via the dr states in the ta p controller. instruction register (ir - 3 bits) the instruction register stores the variou s tap instructions supported by eccram. it is loaded with the idcode instruction (logic 001) at power-up, and when the tap controller is in the test-logic reset and capture-ir states. it is inserted between t di and tdo when the tap controller is in the sh ift-ir state, at which time it can be loaded with a new instruction. however, newly loaded instructions are not ex ecuted until the tap controller ha s reached the update-ir state. the instruction register is 3 bits wide, and is encoded as follows: code (2:0) instruction description 000 extest loads the logic states of all si gnals composing the eccram i/o ring into the boundary scan register when the t ap con troller is in the capture-dr stat e, and inserts the boundary scan register between tdi and tdo when the tap controller is in the shift-dr state. also transfers the contents of the boundary scan register associated with output signals (q, qvld, cq , cq ) directly to their corresponding output pins . however, newly loaded boundary scan register contents do not appear at the output pins until the tap controller has reac hed the update-dr state. also disables all odt. see the boundary scan register description for more information. 001 idcode loads a predefined device- and manufacturer-specific i dentification code into the id register when the tap controller is in the capture-dr state, and inserts the id register between tdi and tdo when the tap controller is in the shift-dr state. see the id register description for more information. 010 sample-z loads the logic states of all si gnals composing the eccram i/o ring into the boundary scan register when the t ap con troller is in the capture-dr stat e, and inserts the boundary scan register between tdi and tdo when the tap controller is in the shift-dr state. also disables all odt. also forces q output drivers to a high-z state. see the boundary scan register description for more information. 011 private reserved for manufacturer use only. 100 sample loads the logic states of all si gnals composing the eccram i/o ring into the boundary scan register when the t ap con troller is in the capture-dr stat e, and inserts the boundary scan register between tdi and tdo when the tap controller is in the shift-dr state. see the boundary scan register description for more information. 101 private reserved for manufacturer use only. 110 private reserved for manufacturer use only. 111 bypass loads a logic 0 into the bypass register when the t ap controller is in the capture-dr state, and inserts the bypass register b etw een tdi and tdo when the tap controll er is in the shift-dr state. see the bypass register descr iption for more information.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 35/39 ? 2015, gsi technology bypass register (dr - 1 bit) the bypass register is one bit wide, and provides the minimum leng th serial path between tdi and tdo. it is loaded with a logic 0 when the bypass instruction has been loaded in the instruction register and the tap controller is in the captur e-dr state. it is inserted between tdi and tdo when the bypass instruction has been loaded into the instruction register and the tap controller is in the shift-dr state. id register (dr - 32 bits) the id register is loaded with a pred etermined device- and manuf acturer-specific identificati on code wh en the idcode instruction has been loaded into the instru ction register and the tap cont roller is in the capture-dr state. it is inserted bet ween tdi and tdo when the idcode instruction ha s been loaded into the instruction regi ster and the tap controller is in the shift-dr state. the id register is 32 bits wi de, and is encoded as follows: see bsdl model (31:12) gsi id (11:1) start bit (0) xxxx xxxx xxxx xxxx xxxx 0001 1011 001 1 bit 0 is the lsb of the id register, and bit 31 is the msb. when the id register is selected, tdi seri ally shifts data into the msb, and the lsb serially shifts data out through tdo. boundary scan register (dr - 129 bits) the boundary scan register is equal in length to the number of active sign al connections to the eccram (excluding the tap pins) plus a number of place holder locations reserved for functio nal and/or density upgrades. it is loaded with the logic stat es of all signals composing the eccram?s i/o ring when the extest, sample, or sample-z instruction ha s been loaded into the instruction register and the tap controller is in the capture-dr state. it is inserted between tdi and tdo when the extest, sample, or sample-z instruction has been load ed into the instruction register and the tap controller is in the shift-dr state. additionally, the conten ts of the boundary scan register associ ated with the eccram outputs (q, qvld, cq, cq ) are driven directly to the corresponding eccram output pins when th e extest instruction is select ed. however, after the extest instruction has been selected, any new data loaded into boundary scan register when the tap cont roller is in the shift-dr state does not appear at the output pins until the tap controller ha s reached the update-dr state. the value captured in the boundary scan register for nu pins is determined by the external pin state. the value captured in the bou ndary scan register for nc pins is 0 regardless of the extern al pin state. the value captured in the internal cell (bit 129) is 1. output driver state during extest extest allows the internal cell (bit 129) in the boundary scan reg i ster to control the state of q drivers. that is, when bit 12 9 = 1, q drivers are enabled (i.e., driving high or low), and when bit 129 = 0, q drivers are disabled (i.e., forced to high-z stat e). see the boundary scan register section for more information. odt state during extest and sample-z odt on all inputs is disabled during extest and sample-z.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 36/39 ? 2015, gsi technology boundary scan register bit order assignment the table below depicts the order in which the bits are arranged in the boundary scan register. bit 1 is the lsb and bit 129 is the msb. when the boundary scan regi ster is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. bit pad bit pad bit pad bit pad bit pad 1 7l 29 12f 57 12w 85 1t 113 1c 2 7k 30 11g 58 10w 86 4r 114 3c 3 9l 31 13g 59 8v 87 2r 115 2b 4 9k 32 10g 60 9u 88 3p 116 4b 5 8j 33 12g 61 8t 89 1p 117 5a 6 7h 34 11h 62 9r 90 4p 118 6a 7 9h 35 13h 63 8p 91 2p 119 6b 8 7g 36 10j 64 9n 92 3n 120 6c 9 8g 37 12j 65 8m 93 1n 121 5d 10 9f 38 13k 66 6m 94 4m 122 6e 11 8e 39 13l 67 7n 95 2m 123 5f 12 7d 40 11l 68 5n 96 3l 124 6g 13 9d 41 12m 69 7p 97 1l 125 5h 14 8c 42 10m 70 6p 98 1k 126 6j 15 7b 43 13n 71 5r 99 2j 127 5k 16 8b 44 11n 72 6t 100 4j 128 5l 17 9b 45 12p 73 7u 101 1h 129 internal 18 7a 46 10p 74 5u 102 3h 19 9a 47 13p 75 6v 103 2g 20 10b 48 11p 76 6w 104 4g 21 12b 49 12r 77 7y 105 1g 22 11c 50 10r 78 4w 106 3g 23 13c 51 13t 79 2w 107 2f 24 10d 52 11t 80 3v 108 4f 25 12d 53 12u 81 1v 109 1e 26 11e 54 10u 82 4u 110 3e 27 13e 55 13v 83 2u 111 2d 28 10f 56 11v 84 3t 112 4d
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 37/39 ? 2015, gsi technology 260-pin bga package drawing (package gk) ball pitch: ball diameter: substrate thickness: mold thickness: 131211109876543 a b c d e f g h j k l m n p r t u v w 13.20 ? 0.05 14.00 ? 0.05 22.00 ? 0.05 17.40 ? 0.05 pin #1 corner 21 y seating plane heat spreader 1.00 12.00 19.00 1.00 a b 0.05(4x) 1.00 0.60 0.51 ? 0.50 + 0.03 2.10 + 0.2/?0.3 0.40~0.60 c 0.06 0.10 c // 1.09 ref 0.51 ref 0.05 4?r0.5 (max) ? 0.50~ ? 0.70(260x) ? 0.08 s ? 0.22 s c c a s b s 0.15 c
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 38/39 ? 2015, gsi technology ordering information ? gs i sigmaquad-ive eccram org part number type package speed (mhz) t a 8m x 18 gs81314ld19gk-933 sigmaquad-ive b4 rohs-compliant 260-pin bga 933 c 8m x 18 gs81314ld19gk-800 sigmaquad-ive b4 rohs-compliant 260-pin bga 800 c 8m x 18 gs81314ld19gk-933i sigmaquad-ive b4 rohs-compliant 260-pin bga 933 i 8m x 18 gs81314ld19gk-800i sigmaquad-ive b4 rohs-compliant 260-pin bga 800 i 4m x 36 gs81314ld37gk-933 sigmaquad-ive b4 rohs-compliant 260-pin bga 933 c 4m x 36 GS81314LD37GK-800 sigmaquad-ive b4 rohs-compliant 260-pin bga 800 c 4m x 36 gs81314ld37gk-933i sigmaquad-ive b4 rohs-compliant 260-pin bga 933 i 4m x 36 GS81314LD37GK-800i sigmaquad-ive b4 rohs-compliant 260-pin bga 800 i note: c = commercial t emperature range. i = industrial temperature range.
gs81314ld19/37gk-933/800 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.02 3/2016 39/39 ? 2015, gsi technology revision history rev. code types of changes format or content revisions gs81314ld1937gk_r1 ? ? creation of new rl=5 -specific datasheet with no bank rest rictions. gs81314ld1937gk_r1.01 content ? changed -833 speed bin to -800, and reduced the v dd (min) spec to 1.15v (in order to support 1.2v nominal). gs81314ld1937gk_r1.02 content ? removed ?preliminary? from data sheets. ?

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